发明名称 TRI-STATE BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a tri-state buffer circuit with a small area and also with small delay and an integrated circuit having the tri-state buffer circuit. SOLUTION: A tri-state buffer is constituted of a small number of components by coupling a prestage circuit of the tri-state buffer with the tri-state buffer. The tri-state buffer has the small area, in addition to that, has an ability for compensating delay difference between rise and fall of a signal and delay of the entire circuit is reduced by using the ability. A circuit in the case of using a multiplexer is specifically constituted as the most useful prestage circuit. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004153690(A) 申请公布日期 2004.05.27
申请号 JP20020318490 申请日期 2002.10.31
申请人 NEC CORP 发明人 NAKATANI SHOGO
分类号 H03K17/00;H03K17/687;H03K19/0175;H03K19/0948;(IPC1-7):H03K19/017;H03K19/094 主分类号 H03K17/00
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