| 摘要 |
A Phase-Locked Loop with multiphase clocks with a main loop comprising a Phase Frequency Detector (1), a Main Charge Pump (2), a Main Loop Filter (3), a Multi-Phase Voltage Controlled Oscillator (4) and a Phase-switching Fractional Divider (5), coupled in series, a calibration loop comprising a Calibration Charge Pump (6), a multiplexer (7) and Y Calibration Loop Filters (8), with Y being an integer, a Control Logic (9) arranged to control said Phase-Switching Fractional Divider (5) and said multiplexer (7), and a Reference Frequency Signal (10) applied to said Phase Frequency Detector (PFD)(1) and a calibration signal (11) applied to said calibration loop, characterised in that the main loop comprises a Phase-adjusting block (12) coupled with a demultiplexer (13), wherein said Phase-adjusting block is arranged to receive correction signals from said calibration loop and said multiplexer is controlled by said Control Logic (9) <IMAGE>
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