| 摘要 |
<p>A data processing circuit comprising a circuit section (100) having a first clock signal Sc1, a circuit section (200) having a second clock signal Sc2 and receiving a data signal Sd and the first clock signal Sc1 from the circuit section (100), a circuit section (152) for comparing the phases of the second clock signal Sc2 and the first clock signal Sc1 at the circuit section (200), and a VCO (151) for controlling the phase of the first clock signal based on the comparison result from the phase comparison circuit section.</p> |
