发明名称 Clock extraction device to achieve extraction of different clocks corresponding to a plurality of input ports respectively with a common phase locked loop
摘要 Incoming serial data is quantized by 3-times oversampling to obtain a first datastream. By the EXOR of adjacent bits in the datastream, a second datastream which specifies transient points in the first datastream is produced from the first datastream. Reference is made to the third bit from each transient point in the second datastream and to bits positioned on each side of the third bit. If there exists no transient point in any one of these two bits, then the third bit is a boundary. On the other hand, if there exists a transient point in either of the two bits, the bit where the transient point exists is a boundary. In this way, a third datastream is produced. Then, the time-series EXOR of the third datastream and a clock bitstream is performed to produce a final clock bitstream.
申请公布号 US6735710(B1) 申请公布日期 2004.05.11
申请号 US20000655717 申请日期 2000.09.05
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 YOSHIKAWA TAKEFUMI
分类号 H03L7/099;H04L7/033;H04L7/04;(IPC1-7):G06F1/04 主分类号 H03L7/099
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