Nonmaskable interrupt workaround for a single exception interrupt handler processor

摘要

A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.