| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To enhance reliability of resynchronized data by suppressing a jitter of a high-speed serial signal transmitted at a long distance. <P>SOLUTION: A shift register series-parallel circuit 03 parallelizes an input data signal (b). Input data expanding circuits 05-06 extend input parallel data signals d-e in a predetermined clock length in a time base direction and output expanding data signals g-h. An input pattern detector circuit 04 sends an input capturing signal (i) so as to capture data near a center of a change point of expanding data signals g-h. A resynchronization data capturing signal generator circuit 13 synchronizes an input capturing signal (z) with an output clock signal (n), and latches the signal (z). Data resynchronizing circuits 11-12 latch the signals g-h at timing of a recapturing signal l. A data delay circuit 18 holds the data until bit trains of an idle pattern are all output completely. A data selector circuit 19 synchronizes with the idle pattern and outputs an output data signal (w). <P>COPYRIGHT: (C)2004,JPO</p> |
