发明名称 Method and device for testing bit errors
摘要 In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial signal for test is converted into parallel signals corresponding to channels for a plurality of measured devices and a redundant channel to be demultiplexed for the measured devices, a passing signal through the redundant channel is converted into a channel determination signal for specifying an alignment of the measured devices, output signals of the measured devices and the channel determination signal are multiplexed corresponding to a demultiplexing mode, and bit errors are measured from the multiplexed signals and measured devices concerning the bit errors are detected from the channel determination signal.
申请公布号 US2004073860(A1) 申请公布日期 2004.04.15
申请号 US20030686693 申请日期 2003.10.15
申请人 NISHIOKA NAONORI 发明人 NISHIOKA NAONORI
分类号 H04L1/20;H04L1/24;(IPC1-7):H04L1/00;G06F11/00;G06F11/30;G08C25/00;H03M13/00 主分类号 H04L1/20
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