发明名称 |
Semiconductor device with clock generation circuit |
摘要 |
An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.
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申请公布号 |
US6720807(B1) |
申请公布日期 |
2004.04.13 |
申请号 |
US20030377738 |
申请日期 |
2003.03.04 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
KUBO TAKASHI;IWAMOTO HISASHI |
分类号 |
G06F1/04;G06F1/10;H03K19/00;H03K19/0175;H03L7/081;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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