发明名称 System and method enabling efficient cache line reuse in a computer system
摘要 A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.
申请公布号 US2004068616(A1) 申请公布日期 2004.04.08
申请号 US20020263740 申请日期 2002.10.03
申请人 TIERNEY GREGORY E.;VAN DOREN STEPHEN R. 发明人 TIERNEY GREGORY E.;VAN DOREN STEPHEN R.
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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