发明名称 Semiconductor multi-package module having wire bond interconnection between stacked packages
摘要 A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
申请公布号 AU2003272405(A8) 申请公布日期 2004.04.08
申请号 AU20030272405 申请日期 2003.09.15
申请人 CHIPPAC, INC. 发明人 MARCUS KARNEZOS
分类号 H01L23/12;H01L25/10;H01L25/11;H01L25/18 主分类号 H01L23/12
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