发明名称 Dram bit lines
摘要 A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.
申请公布号 US6716715(B2) 申请公布日期 2004.04.06
申请号 US20010044307 申请日期 2001.10.26
申请人 STMICROELECTRONICS S.A. 发明人 CIAVATTI JEROME
分类号 H01L21/60;H01L21/8242;(IPC1-7):H01L21/20 主分类号 H01L21/60
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