| 摘要 |
The invention relates to a three-dimensional chip assembly, in which the interchip contact surfaces (15) are divided into contact surface zones (9) for vertically contacting chip layers (1-3, 1'-3') that are arranged one above the other. The size of each contact surface zone (9) preferably corresponds to the size of the contact element, which is used to create the contact with an upper chip layer (1'-3'). Only the contact surface zones (9) that are actually contacted are switched to "active" by means of a control logic. No voltage is therefore applied to the remaining contact surface zones. The crosstalk behaviour of the interchip connection in relation to metallized sections of adjacent chip layers is thus significantly improved. |
