发明名称 |
Time synthesis for power optimization of high performance circuits |
摘要 |
A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.
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申请公布号 |
US2004060016(A1) |
申请公布日期 |
2004.03.25 |
申请号 |
US20030665521 |
申请日期 |
2003.09.22 |
申请人 |
PATRA PRIYADARSAN;CHAPPELL BARBARA |
发明人 |
PATRA PRIYADARSAN;CHAPPELL BARBARA |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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