| 摘要 |
A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.
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