发明名称 |
Method of manufacturing ESD protection structure |
摘要 |
A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.
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申请公布号 |
US2004058502(A1) |
申请公布日期 |
2004.03.25 |
申请号 |
US20030670918 |
申请日期 |
2003.09.24 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
CAI JUN;HUA GUANG PING;SONG JUN;LO KENG FOO |
分类号 |
H01L27/02;(IPC1-7):H01L21/331;H01L21/822 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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