发明名称 |
SOLDER-FILL OF SEMICONDUCTOR PACKAGE PROCESS AND FABRICATING METHOD THEREOF |
摘要 |
PURPOSE: A solder-fill of a semiconductor package process and a fabricating method thereof are provided to form an under-fill and mount easily a semiconductor chip on a substrate by performing only a thermal process without using a dispenser. CONSTITUTION: A solder-fill(130) of a semiconductor package process includes an under-fill material(134) and a solder bump material(132). The under-fill material(134) is used as a filling material inserted between a semiconductor chip and a substrate in the semiconductor package process. The solder bump material(132) is formed with a shape of column corresponding to a shape of a pad of the semiconductor chip in the under-fill material(134). The height of the solder bump material(132) is equal to the height of the under-fill material(134).
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申请公布号 |
KR20040025378(A) |
申请公布日期 |
2004.03.24 |
申请号 |
KR20020057331 |
申请日期 |
2002.09.19 |
申请人 |
SEOUL NATIONAL UNIVERSITY |
发明人 |
LEE, HO YEONG |
分类号 |
H01L21/56;(IPC1-7):H01L21/56 |
主分类号 |
H01L21/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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