发明名称 |
Integrated circuit chip with high-aspect ratio vias |
摘要 |
An integrated circuit is provided with high-aspect ratio vias in which the upper channel after lining with an adhesion/barrier layer is used as a collimator with a via entrant angle of greater than about 70 degrees during the ionized metal plasma deposition of the seed layer over the adhesion/barrier layer. This results in a seed layer with reduced overhang in the vias enhancing the subsequent filling of the vias by a conductive layer and preventing the formation of voids in the vias.
|
申请公布号 |
US6710447(B1) |
申请公布日期 |
2004.03.23 |
申请号 |
US20000579340 |
申请日期 |
2000.05.25 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
NOGAMI TAKESHI |
分类号 |
H01L23/522;H01L23/532;(IPC1-7):H01L23/48 |
主分类号 |
H01L23/522 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|