发明名称 |
Prefetching data in a computer system |
摘要 |
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
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申请公布号 |
US2004054853(A1) |
申请公布日期 |
2004.03.18 |
申请号 |
US20020244250 |
申请日期 |
2002.09.16 |
申请人 |
SPRANGLE ERIC A.;ROHILLAH ANWAR Q. |
发明人 |
SPRANGLE ERIC A.;ROHILLAH ANWAR Q. |
分类号 |
G06F9/00;G06F9/38;G06F12/00;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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