| 摘要 |
In a parallel interface bus structure (FIG. 4, 110), a determination is made as to the number of signals will be allowed to change state during a clock period. This determination is made in accordance with the power consumption requirements of the particular computer communications system (FIG. 1). A processor (FIG. 4, 120) ascertains the number of clock periods required to perform the changes in state of an information word based on the power consumption requirements and the number of changes in state required to complete the information word. The processor (120) then makes the changes using the least number of clock periods and transmits a data ready indication when the process is complete. This results in fewer clock periods required to transmit an information word while adhering to power consumption requirements.
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