发明名称
摘要 A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem , a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.
申请公布号 JP2004507802(A) 申请公布日期 2004.03.11
申请号 JP20010573248 申请日期 2000.05.15
申请人 发明人
分类号 G06F15/173;G06F15/177;G06F15/80;(IPC1-7):G06F15/173 主分类号 G06F15/173
代理机构 代理人
主权项
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