发明名称 |
Package design and method of manufacture for chip grid array |
摘要 |
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
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申请公布号 |
US2004046257(A1) |
申请公布日期 |
2004.03.11 |
申请号 |
US20020236337 |
申请日期 |
2002.09.06 |
申请人 |
ADVANPACK SOLUTIONS PTE.LTD. |
发明人 |
HWEE TAN KIM;PEREZ ROMAN;LAU KEE KWANG;CHEW ALEX;DIMAANO ANTONIO |
分类号 |
H01L23/31;H01L23/36;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L23/31 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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