发明名称 RC netlist reduction for timing and noise analysis
摘要 A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided.
申请公布号 US6704911(B2) 申请公布日期 2004.03.09
申请号 US20010034591 申请日期 2001.12.28
申请人 SUN MICROSYSTEMS, INC. 发明人 YANG XIAO-DONG
分类号 G06F17/50;(IPC1-7):G06F17/10 主分类号 G06F17/50
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