发明名称 |
Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system |
摘要 |
A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
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申请公布号 |
US2004039880(A1) |
申请公布日期 |
2004.02.26 |
申请号 |
US20020226478 |
申请日期 |
2002.08.23 |
申请人 |
PENTKOVSKI VLADIMIR;GARG VIVEK;IYER NARAYANAN S.;KESHAVA JAGANNATH |
发明人 |
PENTKOVSKI VLADIMIR;GARG VIVEK;IYER NARAYANAN S.;KESHAVA JAGANNATH |
分类号 |
G06F12/08;(IPC1-7):G06F12/00;G06F12/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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