Circuit for enhancing scan testing capability of a digital IC tester

摘要

A circuit for enhancing scan testing capability of a digital IC tester. The circuit is connected between the digital IC tester and a DUT. The circuit comprises a binary counter receiving a clock signal from the digital IC tester to sequentially output addresses, a memory device storing scan-in and expected scan-out data, and receiving the addresses from the binary counter to output the scan-in data to a scan chain and the expected scan-out data corresponding to the addresses, a delay circuit receiving the clock signal from the digital IC tester and outputting the delayed clock signal to the scan chain, and a comparator receiving scan-out data from the scan chain and the expected scan-out data from the memory device, and outputting comparison results to the digital IC tester