| 摘要 |
<P>PROBLEM TO BE SOLVED: To easily change duty ratio of a pulse signal. <P>SOLUTION: This dutycycle change circuit is provided with: a D type FF (flip flop) 12 which changes level of output signal to high at every time wherein a pulse signal is input in a clock terminal; a diode 15 whose cathode terminal is connected with an output terminal of the D type FF; a charge circuit 18 which is interposed between an anode terminal of the diode and a DC power source and charged by the DC power source in term that level of an output signal of the D type FF is maintained to be high and in which charged electric charges are discharged to an output terminal side of the D type FF via the diode when the level of an output signal is changed to low; a Schmidt circuit 19 which is connected with the anode terminal of the diode, to which charge voltage of the charge circuit which is charged by the DC power source is applied and which sends a reset signal to the D type FF when the charge voltage reaches a threshold value; and a buffer circuit 13 which outputs an output signal of the D type FF as an output pulse signal. <P>COPYRIGHT: (C)2004,JPO |
