摘要 |
A clock signal distributor circuit for maintaining a phase relationship between one or more remote operating nodes and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb for each remote node. The clock signal distributor circuit comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on the sense path. |