SYSTEM AND METHOD FOR DESIGNING MASK AND PROGRAM FOR CAUSING COMPUTER TO PERFORM MASK DESIGN PROCESSING OR LAYOUT DESIGN PROCESSING

摘要

PROBLEM TO BE SOLVED: To provide a mask design system where processing time for adjusting an opening rate is shortened.

SOLUTION: The mask design system of a semiconductor integrated circuit comprises a layout design part and a layout verification part. The layout design part is provided with a layout generation part generating a chip layout, an opening rate calculation part calculating an opening rate, an opening rate verification part judging whether the opening rate is within a prescribed reference value range on a mask pattern layer or not, a dummy pattern arranging part arranging a dummy pattern in the mask pattern layer when the opening rate of the mask pattern layer is smaller than a lower limit value of the reference value range, and a dummy pattern deletion part deleting the dummy pattern from the mask pattern layer when the opening rate of the mask pattern layer is larger than an upper limit value of the reference value range.

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