| 摘要 |
A clock recovery circuit comprises a phase comparator detecting phase differences between input data and sampling clocks and outputs them as pulse signals of two values of advanced and delayed, a low-pass filter reducing frequencies of the pulse signals outputted from the phase comparator and outputs reduced frequencies, a control signal generator monitoring the reduced frequencies and generates a phase control signal used to adjust the phase of each sampling clock to be small or large based on the ratio of the advanced and delayed signals, a phase interpolator adjusting the phase of each sampling clock upon receiving the phase control signal, and a frequency divider dividing the sampling clock having the adjusted phase by a predetermined frequency division ratio to output it, and controls the low-pass filter and control signal generator based on the frequency divided output.
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