| 发明名称 |
Processor-processor synchronization |
| 摘要 |
A first processor executes a transaction targeting a pre-determined address, wherein the transaction is detected by a wait unit that asserts a wait signal to cause the first processor to enter a wait mode. The wait signal is de-asserted when the wait unit receives a signal from another processor or when a system interrupt occurs. |
| 申请公布号 |
EP1387258(A2) |
申请公布日期 |
2004.02.04 |
| 申请号 |
EP20030291922 |
申请日期 |
2003.07.30 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS FRANCE |
发明人 |
CHAUVEL, GERARD;LASSERRE, SERGE |
| 分类号 |
G06F9/30;G06F9/318;G06F9/32;G06F12/02;G06F12/08;G06F12/12;G06F15/00 |
主分类号 |
G06F9/30 |
| 代理机构 |
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代理人 |
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