发明名称 |
Computer program for encoding digital data |
摘要 |
Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.
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申请公布号 |
US6686855(B2) |
申请公布日期 |
2004.02.03 |
申请号 |
US20030400500 |
申请日期 |
2003.03.28 |
申请人 |
VICTOR COMPANY OF JAPAN, LTD. |
发明人 |
HAYAMI ATSUSHI;KUROIWA TOSHIO |
分类号 |
G11B20/14;G11B20/18;H03M5/14;H03M7/46;(IPC1-7):H03M7/00 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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