发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit whereby frequency deviation is eliminated in a produced signal while stabilizing its operation when a reference signal is switched. <P>SOLUTION: The PLL circuit includes: a phase comparator 1; an integrator circuit 2; a voltage-controlled oscillator 3; a frequency divider circuit 4; a selection circuit 7 for selecting either of two received reference signals 5, 6; and a phase difference elimination circuit 8 having a function of canceling a phase difference between the two reference signals, and the phase difference elimination circuit 8 includes: a signal input detection circuit 9 for monitoring the two received reference signals 5, 6 to detect whether or not the two received reference signals 5, 6 exist; a phase difference presence detection circuit 10 for detecting the presence / absence of the phase difference between the two received reference signals 5, 6; and a delay circuit 11 for delaying either of the two received reference signals 5, 6. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004023470(A) 申请公布日期 2004.01.22
申请号 JP20020176157 申请日期 2002.06.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 KONNO HIDEAKI
分类号 H03L7/00;H03L7/08 主分类号 H03L7/00
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