| 摘要 |
PROBLEM TO BE SOLVED: To construct a new system that can be configured at a low cost without using a conventional known hierarchically structured bus system and can utilize an efficient bus. SOLUTION: A high-speed processor includes a shared bus, a plurality of bus masters are respectively and directly connected to the shared bus, and a plurality of bus slaves are respectively connected. A bus arbitration circuit (1307) determines the slower one as a bus cycle period between the fastest period accessible to a bus slave and the fastest period when the shared bus can operate, surely determines the right of using the bus for every bus cycle of the shared bus surely for each of the bus cycle, and gives a use permission signal to a bus master in one bus cycle unit. In addition, an external memory interface circuit (1314) determines whether addresses issued by the bus masters correspond to any region of the shared bus in each bus cycle, refers to a bus cycle length register for each of the region and gives a bus cycle end signal to a bus master. COPYRIGHT: (C)2004,JPO
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