发明名称 Incrementer/decrementer circuit
摘要 Provided is an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal is connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal include at least one bit based solely on a corresponding bit in the quantity and at least one bit based solely on a value of the increment/decrement signal.
申请公布号 US6678711(B1) 申请公布日期 2004.01.13
申请号 US20000665924 申请日期 2000.09.20
申请人 LSI LOGIC CORPORATION 发明人 KALARI SUBBA RAO
分类号 G06F7/50;(IPC1-7):G06F7/50 主分类号 G06F7/50
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