| 摘要 |
PROBLEM TO BE SOLVED: To facilitate a bus master device of a high-order bus side, quickly migrating to a next process, when an successive write cycle from a high-order bus to a low-order bus is executed. SOLUTION: A high-order bus slave circuit 22, which is connected to the high-order bus 17, and a low-order bus master circuit 23, which is connected to the low-order bus 18, are allocated in a bus adapter device 21 allocated between the high-order bus 17 and the low-order bus 18, and a FIFO memory 24 and an unpacked register 25 are connected between them. The low-order bus master circuit 23 independently transfers data sequentially to the low-order bus 18, when the data for writing are stored in the FIFO memory 24. Thus, a master device at the high-order bus 17 side is removed of the restrictions, at the time the information is stored in the FIFO memory 24. COPYRIGHT: (C)2004,JPO
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