发明名称 DATA SYNCHRONIZATION METHOD IN DIGITAL SYSTEM HAVING A PLURALITY OF SELF-ADAPTIVE INTERFACES
摘要 <p><P>PROBLEM TO BE SOLVED: To control an interface in order to automatically acquire a minimum cycle latency time while maintaining synchronous data arrival among a plurality of self-adapting interfaces. <P>SOLUTION: An independent self timing regulation interface 108 skews data bits and can make them arrive in a minimum cycle range. But, unless they arrive in all the interface with an identical cycle, symmetric parallel design cannot perform functions properly. A latest cycle is determined by the use of a regulation pattern in which data are received by an elastic interface, and all target cycles of the interface 108 are computed so as to match the latest cycle. The target cycle is reflected in design and data are received in synchronizing. A test for confirming data arrival in synchronizing is performed. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004007681(A) 申请公布日期 2004.01.08
申请号 JP20030138148 申请日期 2003.05.16
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CHEN JONATHAN Y;MEANEY PATRICK J;SCARPERO WILLIAM J JR
分类号 G06F13/42;H04L7/00;H04L7/04;H04L7/08;(IPC1-7):H04L7/00 主分类号 G06F13/42
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