| 发明名称 |
Built-in debug feature for complex VLSI chip |
| 摘要 |
An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.
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| 申请公布号 |
US2004004279(A1) |
申请公布日期 |
2004.01.08 |
| 申请号 |
US20020190933 |
申请日期 |
2002.07.08 |
| 申请人 |
LSI LOGIC CORPORATION |
发明人 |
LEUNG HO-MING;ZHANG FAN;CHU CHIU-TSUN;CHANG GARY |
| 分类号 |
G01R31/317;G01R31/3185;(IPC1-7):H01L23/495;H01L23/053;H01L23/12;H01L23/48;H01L23/52 |
主分类号 |
G01R31/317 |
| 代理机构 |
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代理人 |
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