| 摘要 |
Disclosed is an offset voltage cancellation circuit that can quickly cope with a change in the state and can cancel an offset voltage for differential signals. Peak voltages VP1 and VP2 of differential input signals VA1 and VA2 are retained in capacitors 12 of peak detectors 101 and 102. An adder 201 adds the differential input signal VA1 to the peak voltage VP2 to obtain a differential output signal VC1, while an adder 202 adds the differential input signal VA2 to the peak voltage VP1 to obtain a differential output signal VC2. The differential output voltages VC1 and VC2 are transmitted to a peak level reset unit 30 to generate a reset signal RST that is consonant with the potential difference, and the reset signal RST is transmitted to the gates of NMOSes 14 of the peak detectors 101 and 102. When an offset occurs between the differential output signals VC1 and VC2, the level of the reset signal RST is increased, and the NMOSes 14 are rendered conducive. Then, the peak voltages VP1 and VP2 stored in the capacitors 12 are reset.
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