发明名称 Timing scheme for semiconductor memory devices
摘要 A semiconductor memory device includes at least one memory cell for storing digital data. A local sense amplifier is operably coupled to the at least one memory cell for receiving a first signal representative of the digital data stored in the at least one memory cell, and outputting a second signal representative of the received first signal in response to a first strobe signal. A global sense amplifier is operably coupled to the local sense amplifier for receiving the second signal, and outputting a third signal representative of the received second signal in response to a second strobe signal. Dummy circuitry is provided for-enabling generation of the first and second strobe signals.
申请公布号 US6667912(B1) 申请公布日期 2003.12.23
申请号 US20020078313 申请日期 2002.02.18
申请人 LSI LOGIC CORPORATION 发明人 MONZEL CARL A.
分类号 G11C7/06;G11C7/14;G11C7/18;(IPC1-7):G11C7/00;G11C7/02 主分类号 G11C7/06
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