| 摘要 |
In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36 , which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40 . During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40 , so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40 , the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited. Each graded SiGe layer is permitted to relax by pile-ups of dislocations, but the uniform SiGe layers 40 prevent the pile-ups of dislocations from extending out of the graded SiGe layers 38 . Furthermore each of the subsequent annealing steps ensures that the previously applied graded and uniform SiGe layers 38 and 40 are fully relaxed in spite of the relative thinness of these layers. As a result the dislocations are produced substantially independently within successive pairs of layers 38 and 40 , and are relatively evenly distributed with only small surface undulations 40 being produced. Furthermore the density of threading dislocations is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice which can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons. |
