| 摘要 |
A clock generation device (100) includes a delay-locked loop (104) and plurality of programmable counters (106). The plurality of programmable counters are coupled to delay-locked loop. Each of the programmable counters has a separate output (114, 116, 118, 120). The delay-locked loop is configured to generate a plurality of phase delay line outputs (110). A hard drive includes the delay-locked loop and the programmable counters, which generate multiple timing signals such as read, write, servo, and system timing signals. The method of generating a plurality of timing pulses through the programmable counters. |
