| 摘要 |
The present invention pertains to automated technology dependent transformations in Silicon-On-Insulator (SOI) during the digital design synthesis, the transformations include the steps of receiving input design specification in the form of technology independent specification and/or interconnected structural blocks, where the structural blocks have been described as a library of standard-cells; performing the technology dependent transformations during the digital design synthesis, resulting in interconnected SOI standard-cells from a SOI target library accounting for floating body effects, including floating body effects affecting delays over long periods of simulation time or testing over long times on fabricated SOI library cells, and/or SOI transistor level representations or a combination thereof, transistor sizing and evaluating the standard-cell mapping and/or transistor-level representation for all or portion of the input design specification iteratively to meet delay and/or power constraints for SOI; or during technology dependent transformations in CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and/or transistor-level representation for all or portion of the input design specification, the transistor level type and portion or portions to be represented at the transistor level representation being chosen by a user, transistor sizing and evaluating the combination of said transistor-level representation and/or standard-cell mapping iteratively to meet delay, size and/or power constraints for CMOS.
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