发明名称 |
Output prediction logic circuits with ultra-thin vertical transistors and methods of formation |
摘要 |
Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.
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申请公布号 |
US2003227072(A1) |
申请公布日期 |
2003.12.11 |
申请号 |
US20020164611 |
申请日期 |
2002.06.10 |
申请人 |
FORBES LEONARD;AHN KIE Y. |
发明人 |
FORBES LEONARD;AHN KIE Y. |
分类号 |
H01L21/336;H01L21/8238;H01L27/092;H01L27/118;H01L29/76;H01L31/117;(IPC1-7):H01L31/117 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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