发明名称 |
Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock |
摘要 |
A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.
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申请公布号 |
US2003219043(A1) |
申请公布日期 |
2003.11.27 |
申请号 |
US20020328031 |
申请日期 |
2002.12.26 |
申请人 |
FUJITSU LIMITED |
发明人 |
DOI YOSHIYASU;TAMURA HIROTAKA |
分类号 |
H03K17/00;H03K17/693;H03K19/0185;H04J3/04;H04L25/02;(IPC1-7):H04J3/02 |
主分类号 |
H03K17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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