发明名称 |
Well bias control circuit |
摘要 |
Disclosed is a semiconductor integrated circuit device having a control mechanism 11 for compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit 10 constructed by a CMOS; a delay monitor 21 for simulating a critical path of the main circuit 10 constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 23 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 21 and the PN Vt balance compensation circuit 23 and applying a well bias to the delay monitor 21 and the main circuit 10 so as to compensate the operation speed of the delay monitor 21 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.
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申请公布号 |
US6653890(B2) |
申请公布日期 |
2003.11.25 |
申请号 |
US20020284207 |
申请日期 |
2002.10.31 |
申请人 |
RENESAS TECHNOLOGY CORPORATION |
发明人 |
ONO GOICHI;MIYAZAKI MASAYUKI;ISHIBASHI KOICHIRO |
分类号 |
H01L21/822;G11C11/40;H01L21/8238;H01L27/04;H01L27/092;H03K17/30;H03K19/003;(IPC1-7):G05F1/46 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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