| 摘要 |
1,155,496. Memory matrix circuits. RADIO CORPORATION OF AMERICA. 20 Feb., 1968 [6 March, 1967], No. 8198/68. Heading H3B. A plurality of arrays a, b, c, d in a memory are arranged in pairs the arrays of each pair being energized by common bit drivers D 1 , D 2 and/or common switches S 1 , S 2 for reading and writing. In Fig. 1 only drivers D are common to the arrays of a pair. Magnetic cores M in arrays a and b of a pair are differently orientated with respect to the row and column conductors so that a read current in one array flows in the same direction as a write current in the other. For reading, one of the current switches D 11 , D 12 and one of the voltage switches S 11 , S 12 are closed to energize a bit conductor in array a, while one of the switches D 21 , D 22 and one of the switches S 23 , S 24 are closed to energize a corresponding conductor in array b. The reading operation is followed by a writing operation in which the switches are selectively closed to energize the same row conductors as were energized previously, but with the current flow reversed. An appropriate column conductor 10 is energized simultaneously with the row conductors during the reading and writing operations. Intsead of using two sets of current switches D and four sets of voltage switches S, it is possible to have four of the former and two of the latter, or three of each. Thus in Fig. 4 (not shown) the arrays ot the pair have common switches S, while in Fig. 5 (not shown) they have common drivers D for reading from one array and writing in the other, and common switches S for writing in the first array and reading from the other. The current switches may be transistors. |
