| 摘要 |
For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.
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