发明名称 |
Method of design for testability, test sequence generation method and semiconductor integrated circuit |
摘要 |
Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an n-folded line-up structure and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs. The present invention guarantees high fault efficiency in identifying FFs to replace with scan FFs and achieves a higher compaction rate than conventional technology.
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申请公布号 |
US6651206(B2) |
申请公布日期 |
2003.11.18 |
申请号 |
US20010817057 |
申请日期 |
2001.03.27 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
HOSOKAWA TOSHINORI;OHTA MITSUYASU |
分类号 |
G01R31/3183;G01R31/3185;(IPC1-7):G01R31/28;G06F11/00 |
主分类号 |
G01R31/3183 |
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