发明名称 |
Frequency detector for a phase locked loop system |
摘要 |
A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.
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申请公布号 |
US6642747(B1) |
申请公布日期 |
2003.11.04 |
申请号 |
US20020099529 |
申请日期 |
2002.03.15 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
CHIU HON KIN |
分类号 |
H03D13/00;(IPC1-7):H03D13/00 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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