发明名称 |
Apparatus for controlling packet output |
摘要 |
In a packet scheduler, an arithmetic-operation controlling means designates output ports in a time-sharing manner and a parallel arithmetic operation means performs an arithmetic operation common with the queues of each designated output port to obtain packet output completion due times (evaluation factors) of the top packets of queues of each output port. Intra-port selecting means selects the evaluation factor of a packet that is to be preferentially output for each output port based on the result of the arithmetic operations. Then inter-port selecting means determines one to be most-preferentially output from the top packets selected based on the selected evaluation factors and the bandwidths for the output ports. Therefore, an apparatus for controlling packet output having such a packet scheduler can realize accurately control bandwidths of a plurality of queues, high-speed processing and the reduced size thereby being incorporated in hardware.
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申请公布号 |
US2003202517(A1) |
申请公布日期 |
2003.10.30 |
申请号 |
US20020281366 |
申请日期 |
2002.10.25 |
申请人 |
KOBAYAKAWA TAKAHIRO;YAMASHITA HIROAKI |
发明人 |
KOBAYAKAWA TAKAHIRO;YAMASHITA HIROAKI |
分类号 |
H04L12/56;(IPC1-7):H04L12/56 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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