发明名称 Semiconductor integrated circuit having latching means capable of scanning
摘要 A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.
申请公布号 US6639850(B2) 申请公布日期 2003.10.28
申请号 US20010993603 申请日期 2001.11.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 FUKUDA RYO
分类号 G01R31/28;G11C8/02;G11C8/04;G11C29/02;G11C29/48;(IPC1-7):G11C7/00 主分类号 G01R31/28
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